The present invention relates to a semiconductor memory device; and, more particularly, to a data input circuit for use in a semiconductor memory device.
As well-known in the art, a semiconductor memory device is a semiconductor device for storing a lot of data and providing the stored data. The semiconductor memory device includes a data storage area storing data and an input/output area in which a circuit for outputting the data stored in the data storage area, or delivering inputted data thereto, is disposed. The data storage area is provided with a plurality of unit cells, each of which stores data corresponding to an address. The input/output area is provided with a data input circuit for conveying data provided from outside to the data storage area, a data output circuit for outputting data from the data storage area to the outside, a control circuit for controlling the data input circuit and the data output circuit, and an address input circuit for accepting an address from the outside and forwarding it to the data storage area.
To be more specific, the data input circuit aligns data signals provided from the outside via an input/output pad so that the data storage area can receive them, and then delivers the aligned data signals thereto. For example, in case where the data input/output circuit is operated in 4-bit prefetch, it aligns 4-bit data signals sequentially transferred through the input/output pad to 4-bit parallel data and then provides the same to the data storage area. Further, the data input circuit is connected to a data transfer line, wherein data is conveyed to the data storage area via the data transfer line.
The semiconductor memory device receives or outputs a lot of data during a single data access operation, and is provided with data input circuits corresponding to the number of data received or outputted during a single data access operation. For example, if the semiconductor memory device is designed to accept 16 data during a single data access, it is provided with 16 data input circuits. Normally, the semiconductor memory device can receive or output data of various numbers of bits such as 4, 8, and 16 bits during the single data, and is manufactured to set the number of bits by a certain control. This is because it is effective to set the number of bits, to be received and outputted, depending on the system to which the semiconductor memory device is applied (after it is manufactured).
Since the semiconductor memory device is manufactured to receive data of various numbers of bits like this, the circuit area of an area in which the data input circuit is disposed increases considerably and the circuit becomes too complicated. For example, in case of a semiconductor memory device that is operable in each of X16, X8, and X4 modes, the semiconductor memory device has to be provided with 16 data input circuits. Among these, in X16 mode, all of the 16 data input circuits are operated, in X8 mode, only 8 data input circuits are operated, and in X4 mode, only 4 data input circuits are operated.
More specifically, in X16 mode, all inputted data are conveyed to the data storage area via data transfer lines connected to the corresponding data input circuits. But, in X8 mode, data received through the 8 data input circuits cannot be conveyed directly to the data storage area via data transfer lines connected to the 8 data input circuits. That is, it is required that the inputted data be first transferred to data transfer lines corresponding to addresses of the data, and then conveyed to the data storage area. By doing so, the inputted data can be stored in a designated area. Therefore, the semiconductor memory device must be provided with the 16 data input circuits and also have a path through which the inputted data in X4 and X8 modes can be transferred to designated data transfer lines so that it can operate in all of X16, X8 and X4 modes. Thus, there is a need for lots of lines to embody the path capable of transferring data between the 16 data input circuits. Moreover, because of the above need, an area in which the data input circuits are arranged becomes very complicated.
FIG. 1 is a block diagram of a conventional data input circuit used in a semiconductor memory device. In particular, FIG. 1 shows one example of the semiconductor memory device which is provided with 16 data input circuits, and thus performs 4-bit prefetch operation and operates in X4, X8 and X16 modes, respectively.
Referring to FIG. 1, the semiconductor memory device is provided with 16 data input circuits 10_1 to 10_16. Each of the data input circuits 10_1 to 10_16 receives a corresponding one of data signals DQ<0> to DQ<15>, aligns it to 4-bit parallel data, and provides the same to a data storage area. For example, the data input circuit 10_1 outputs sequentially inputted 4-bit data signals DQ<0> as 4-bit parallel data (see a region A represented by a doted line).
These data input circuits can be classified into 4 types. This is to receive and process data according to each of data input modes, X4, X8 and X16.
The first type of data input circuits are the data input circuits 10_1 to 10_4 that take data signals in X4, X8, and X16 modes. Among these circuits, one data input circuit, for instance, the data input circuit 10_1, is provided with an input latch circuit 11_1, a MUX 12_1 and a global driver 13_1. The input latch circuit 11_1 takes sequentially inputted 4-bit data signals, aligns them to aligned data signals ALG0, and outputs the same. The MUX 12_1 selectively outputs the 4-bit data signals latched by the input latch circuit 11_1 in response to the input mode of X4, X8, or X16. The global driver 13_1 drives four global lines GIO<0> by using the 4-bit data signals from the MUX 12_1. This data input circuit 10_1 receives the data signals in X4, X8, and X16 modes, respectively. A switch S1 provided in the MUX 12_1 is operated in all of X4, X8, and X16 modes, and is selectively turned on in response to an address corresponding to the inputted data. Even though there is illustrated only one switch in the MUX 12_1, 4 switches are necessary to process 4-bit data in parallel.
The second type of data input circuits are the data input circuits 10_5 to 10_8 that receives data signals in X8 and X16 modes. For instance, the data input circuit 10_5 is provided with an input latch circuit 11_5, a MUX 12_5 and a global driver 13_5. The MUX 12_5 is composed of two switches S2 and S3. The switch S2 is selectively turned on in response to an address corresponding to the data inputted to the data input circuit 10_1 in X4 mode, and the switch S3 is selectively turned on in response to an address corresponding to the data inputted to the data input circuit 10_5 in X8 and X16 modes. Even though there are illustrated only two switches in the MUX 12_5, 4 switches are necessary to process 4-bit data in parallel.
The third type of data input circuits are the data input circuits 10_9 to 10_16 that accept data signals in X16 mode. For instance, the data input circuit 10_9 is provided with an input latch circuit 11_9, a MUX 12_9 and a global driver 13_9. The MUX 12_9 is composed of three switches S4, S5 and S6. The switch S4 is selectively turned on in response to an address corresponding to the data inputted to the data input circuit 10_1 in X4 mode. The switch S5 is selectively turned on in response to an address corresponding to the data inputted to the data input circuit 10_1 in X8 mode. And, the switch S6 is selectively turned on in response to an address corresponding to the data inputted to the data input circuit 10_9 in X16 mode. Even though there are illustrated only three switches in the MUX 12_9, 4 switches are necessary to process 4-bit data in parallel.
FIG. 2 shows a detailed block diagram of one of the input latch circuits depicted in FIG. 1, for example, 11_1.
Referring to FIG. 2, the input latch circuit 11_1 is provided with an input buffer 11A, a delay circuit 11B, and a plurality of latch circuits 11C to 11I. The input buffer 11A buffers the data signal received via the data input/output pad, and the delay circuit 11B delays an output of the input buffer 11A. The plurality of latch circuits 11C to 11I latch the data signal in response to rising and falling data strobe signals DQSR and SQSF. The data latched by the latches 11D, 11E, 11H, and 11I are fed to respective next blocks as 4-bit aligned internal data.
In X16 mode, all of the 16 data input circuits 10_1 to 10_16 shown in FIG. 1 receive the data signals. Each of the 16 data input circuits 10_1 to 10_16 aligns each received data signal and outputs it to a global line connected thereto. In X8 mode, the data input circuits 10_1 to 10_8 receive the data signals. The data signals received through the data input circuits 10_1 to 10_8 may be outputted via global lines connected to the circuits 10_1 to 10_8, or via global lines connected to the rest data input circuits 10_9 to 10_16 that do not receive the data signals. This is decided based on an address corresponding to the data signal inputted in X8 mode. Since all the unit cells involved in the data storage area correspond to the 16 global lines connected to the 16 data input circuits, the data signal inputted in X8 must be transferred to the global line connected to the corresponding unit cell depending on the address.
In X4 mode, the data input circuits 10_1 to 10_4 receive the data signals. The data signals received through the data input circuits 10_1 to 10_4 may be outputted via global lines connected thereto, or via global lines connected to the data input circuits 10_5 to 10_16 that do not receive the data signals. To be more specific, the data inputted through the data input circuit 10_1 may be outputted via global line connected to the circuit 10_1, or via global line connected to any one selected from the data input circuits 10_5, 10_9 and 10_13. This selection of the data input circuit is decided based on an address corresponding to the data signal received through the data input circuit 10_1.
As mentioned above, various lines between the data input circuits are required to operate according to all of X16, X8 and X4 modes, and a plurality of switches have to be arranged in MUXs 12_1, 12_5, . . . , and so on. For example, in case of prefetching 4-bit data, 48 lines (4*12) are necessary to selectively provide the data inputted in X4 mode to the 16 data input circuits.
In order to support the number of data that can be received by the semiconductor memory device diversely as discussed above, too many lines and switches are disposed in an area in which the data input circuits are arranged, thereby increasing the circuit area of the semiconductor memory device.